Selected Publication

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Journal
  1. Ing-Chao Lin*, Yun Kae Law, Yuan Xie, "Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes," Accepted by IEEE Trans. on VLSI (TVLSI) System.
  2. Da-Wei Chang, Ing-Chao Lin*, and Lin-Chun Yong, “ROHOM: Requirement-aware Online Hybrid On-chip Memory Management for Multicore Systems”, in IEEE Trans on Computer-Aided Design on Integrated Circuits (TCAD), vol. 36, no. 3, pp. 357 - 369 2017(SCI)(Top Journal in VLSI/EDA) Link
  3. Ing-Chao Lin, Yen-Han Lee, and Sheng-Wei Wang, "Reducing Aging Effect on Ternary CAM", accepted by IEICE Transactions on Electronics   Vol.E99-C   No.7   pp.878-891, 2016
  4. Ing-Chao Lin* and Jeng-Nian Chiou, "High-Endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-Aware Policies", in IEEE Trans. on VLSI (TVLSI) System, vol. 23, no. 10, pp. 2149-2161, Oct. 2015 (SCI)(Top Journal in VLSI/EDA) Link
  5. Ing-Chao Lin*, Yi-Ming Yang, and Cheng-Chien Lin, "High-Performance Low-Power Carry Speculative Addition with Variable Latency", in IEEE Trans. on VLSI (TVLSI) Systems, vol. 23, no. 9, pp. 1591-1603, Sept. 2015 (SCI)(Top Journal in VLSI/EDA) Link
  6. Ing-Chao Lin*, Yu-Hung Cho, and Yi-Ming Yang, "Aging-Aware Reliable Multiplier With Adaptive Hold Logic", in IEEE Trans. on VLSI (TVLSI) Systems vol. 23, no. 3, pp. 544-556, March 2015(SCI)(Top Journal in VLSI/EDA) Link
  7. Da-Wei Chang, Ing-Chao Lin*, Yu-Shiang Chien, Ching-Lun Lin, Alvin W. Y. Su, and Chung-Ping Young, "CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management", in IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 33, pp. 1806-1817, Dec. 2014(SCI)(Top Journal in VLSI/EDA) Link
  8. Kai-Chiang Wu, Ing-Chao Lin*, and Yao-Te Wang, "BTI-aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs", in IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 33, no. 10, pp.1591-1595, Oct. 2014 (SCI)(Top Journal in VLSI/EDA) Link
  9. Ing-Chao Lin*, Shun-Ming Syu, and Tsung-Yi Ho, "NBTI Tolerance and Leakage Reduction using Gate Sizing", in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 11, no. 1, pp. 1-12, Sep. 2014 (SCI) Link
  10. Ing-Chao Lin*, Kuan-Hui Li, Chia-Hao Lin, and Kai-Chiang Wu, "NBTI and Leakage Reduction Using ILP-based Approach" in IEEE Trans. on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 9, pp. 2034-2038, Sep. 2014 (SCI)(Top Journal in VLSI/EDA) Link
  11. Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, and Kuen-Jong Lee, “Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing,” in IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 33, no. 1, pp. 127-138, Jan. 2014 (SCI)(Top Journal in VLSI/EDA) Link
  12. ŸIng-Chao Lin*, Chin-Hong Lin, and Kuan-Hui Li, “Leakage and Aging Optimization Using Transmission Gate-Based Technique”, in IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 32, no. 1, pp. 87-99, Jan. 2013 (SCI)(Top Journal in VLSI/EDA) Link
  13. Po-Hung Chen, Hung-Ming Chen and Ing-Chao Lin, "A Systematic Hardware Sharing Method for Unified Architecture Design of H.264 Transforms", in Mathematical Problems in Engineering, Volume 2015 (2015), Article ID 258613 Link 
  14. N. Dhanwada, R. Bergamaschi2, W. Dungan, I. Nair, P. Gramann, W. Dougherty1 and I.-C. Lin, "Transaction-Level Modeling for Architectural and Power Analysis of PowerPC and CoreConnect based Systems," in Journal of Design Automation for Embedded Systems (SCI) Link
Conference/Workshop/Others
         
  1. Yun Kae Law, Ing-Chao Lin and Cheng-Chien Lin, "Reducing Aging on Scratchpad Memory Using Temporal- and FSM-based Power Management", in International Symposium on VLSI Design, Automation and Test (VLSI DAT), 2017, pp.1-4
  2. Ing-Chao Lin and Shuen-Shiang Yang, “Savior of Device Degradation: Design Automation,” in Design Automation Perspective Challenge, Design Automation Conference (DAC) 2015
  3. Da-Wei Chang, Ing-Chao Lin, Lin-Chun Yong, Chin-Lun Lin, Yu-Shiang Chien and Alvin W.-Y. Su, "Runtime Management of Scratchpad Memory for Hybrid On-Chip Memory", accepted by Workshop on Compiler Techniques and System Software for High-Performance and Embedded Computer, 2015
  4. Jeng-Nian Chiou, Yun-Kae Law, and Ing-Chao Lin, "A 3D Stacked SRAM/STT-RAM Hybrid Cache Architecture with Access-Aware Technique, accepted by Workshop on Compiler Techniques and System Software for High-Performance and Embedded Computer, 2015
  5. Sheng-Wei Wang, Shuen-Shiang Yang and Ing-Chao Lin, “Improving Multicore System Reliability Using Online Cluster-based DVFS Technique,” in International Conference of Computer Aided-Design (ICCAD) Workshop on A Road for EDA Research in the Dark Silicon Era, Nov. 2014
  6. C.-L. Lin, J.-W. Lin, B.-Y. Li, Y.-C. Lin, C.-C. Lin, Alvin W.-Y. Su, D.-W. Chang and I.-C. Lin, “An Novel On-Chip Memory Management Policy for Multi-core System Platform Supporting OpenCL,” in International Conference of Computer Aided-Design (ICCAD) Workshop on Heterogeneous Computing Platforms, Nov. 2014
  7. Ing-Chao Lin, Yao-Te Wang, Shuen-Shiang Yang, and Yi-Luen Wu, “Analyzing The BTI Effect on Multi-bit Retention Registers”, in International Computer Symposium (ICS), pp. 250-259, Dec. 2014
  8. Jeng-Nian Chiou, Yun-Kae Law, and Ing-Chao Lin, “A 3-D Hybrid Cache Design for CMP Architecture with Access-Aware Technique,” in VLSI Design/CAD Symposium, Aug. 2014
  9. Sheng-Wei Wang, Shuen-Shiang Yang and Ing-Chao Lin, “Multicore System Reliability Enhancement Using Online Per-Cluster DVFS,” in VLSI Design/CAD Symposium, Aug. 2014
  10. Chia-Hao Lin and Ing-Chao Lin, “High Accuracy Approximate Multiplier With Error Correction”, In Proceeding of International Computer on Computer Design (ICCD), pp. 33-38, Oct. 2013
  11. Shun-Ming Syu, Jeng-Nian Ciou, and Ing-Chao Lin, “High-Endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-Aware Policy”, in Proceedings of VLSI/CAD Symposium, pp. 97-98, Aug. 2013
  12. Shun-Ming Syu, Yu-Hui Shao, and Ing-Chao Lin, "High-endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-aware Policy," in Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. 19-24, May 2013
  13. Yan-Han Lee, Ing-Chao Lin, and Shen-Wei Wang, “Impact of NBTI and PBTI effects on Ternary CAM,” in Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 38-45, March 2013
  14. Yu-Hung Cho, Ing-Chao Lin, and Yi-Ming Yang, "Aging-aware reliable multiplier design," in Proceedings of SOC Conference (SOCC), pp.322-327, September 2012
  15. Kuan-Hui Li, Ing-Chao Lin Li, and Jia-Hao Lin, "NBTI Mitigation and Leakage Reduction Using ILP" in Proceedings of VLSI/CAD Symposium, Aug. 2012
  16. Yao-Te Wang and Ing-Chao Lin, "Analyzing BTI effects on retention registers," in Proceedings of Asia Symposium of Quality Electronic Design (ASQED), pp.71-77, July 2012
  17. Yu-Hung Cho, Ing-Chao Lin, and Yi-Ming Yang, “NBTI-aware Multiplier Design” in Proceeding of VLSI/CAD Symposium, August 2012
  18. Chin-Hung Lin, Ing-Chao Lin, and Kuan-Hui Li, "TG-based technique for NBTI degradation and leakage optimization," in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 133-138, August 2011
  19. Shi-Qun Zheng, Ing-Chao Lin, and Yu-Hong Jhuo, “Mitigating NBTI using Core Rotation and Scheduled Voltage Scaling“ in Proceedings of VLSI/CAD Symposium, pp. 536-539, Aug. 2011
  20. Chin-Hung Lin, Ing-Chao Lin, and Kuan-Hui Li, “Minimization of Aging and Leakage Using TG-based Technique”, in Proceedings of VLSI/CAD Symposium, pp. 69-72 Aug. 2011
  21. Shi-Qun Zheng, Ing-Chao Lin, and Yen-Han Lee, “Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect”, in Proceedings of Great Lakes Symposium on VLSI (GLSVLSI) pp. 415-418, May 2011
  22. Shi-Qun Zheng and Ing-Chao Lin, "Transaction-level error susceptibility for bus-based System-on-Chip: From single-bit to multi-bit," in Proceedings of International Computer Symposium (ICS), pp.670-675, Dec 2010
  23. Ing-Chao Lin and Vijaykrishnan Narayanan, "System Level Power and Reliability Modeling," Ph.D. Forum, Design, Automation and Test in Europe Conference and Exhibition, April 2007 (DATE)
  24. Ing-Chao Lin, Suresh Srinivasan, Vijaykrishnan Narayanan, Nagu Dhanwada, "Transaction Level Error Susceptibility Model for Bus Based SoC Architectures," in Proceedings of International Symposium on Quality Electronic Design (ISQED), March 2006
  25. Ing-Chao Lin and Vijaykrishnan Narayanan, "Transaction Level Power Modeling for PCI Express," in TECHCON, Oct. 2005 (TECHCON)
  26. Nagu Dhanwada, Ing-Chao Lin and Vijaykrishnan Narayanan, "A Power Estimation Methodology for SystemC Transaction Level Models," in Proceedings of International Conference on Hardware/Software Codesign and System Synthesis, September 2005 (CODES+ISSS)
  27. Nagu Dhanwada, R. Bergamaschi, W. Dungan, I. Nair, W. Dougherty, Y. Shin, S. Bhattacharya, I. Lin, J. Darringer, S. Paliwa1, "Simultaneous Exploration of Power, Physical Design and Architectural Performance Dimensions of the SoC Design Space using SEAS", in IP Based SoC Design Forum & Exhibition, Dec 2004 (IP/REUSE)
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