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make

What is 'make' ?
  • ‘Make’ is an auxiliary tool used to compile and link code, libraries, header files and other resource files to produce the final application program..
The advantage of ‘make’
  • Simplify the commands when compiling.
  • If modifying some source code files, ‘Make’ will only compile the changed files, not alter other object file.
  • Finally in accordance with dependencies to update the executable file.
How to use ‘make’ 
  • You must write a file called the makefile .
  • The file describes the relationships among files in your program and provides commands for updating each file.
  • In a program, the executable file is updated from object files. 
  • Object files are made by compiling source files.
‘make’ usage
  • Usage:make [options] [target]… 
  • options:
-h        :Print all options of ‘make’.
-C DIR    :Change to DIR before doing anything.
-f FILE   :Read FILE as a makefile.
-i      :Ignore errors from commands.
-I DIR    :Search DIR for included makefiles
-k        :Keep going when some targets can’t be made.
-n        :Don’t actually run any commands;just print them.
-s        :Don’t echo commands.
-t        :Touch targets instead of remaking them.
-w        :Print the current directory.
-W FILE   :Consider FILE to be infinitely new.

Rule Syntax of Makefile
target : dependency
<tab> command…

  • target:Usually be file names,such as .EXE or OBJ files. Also be the name of an executable action, such as ‘clean’.
  • dependency:The files are used to generate the target. A target may contain more than one dependency. 
  • command:The executable action of ‘make’ can be any shell commands. A rule may contain multiple commands, but a line contains only one command.Commands start with ‘Tab’ character.
Example 1
editor : main.o text.o
gcc -o editor main.o text.o 
main.o : main.c def.h 
gcc -c main.c 
text.o : text.c com.h 
gcc -c text.c 
clean : 
rm main.o text.o 
Lab1
  • Write a file called main.cc which prints “This is Lab1.”
  • Refer to Example1, edit Makefile using the above simple syntax to compile main.cc
  • Execute ‘make’ to produce the executable file.
How ‘make’ Processes a Makefile
  • $ make
  • It reads the Makefile in the current directory and  begins processing the rules.
  • By default, it refers to the target –– all, and according to its dependencies to create targets. 
  • If no ‘all’, it takes the first target in the Makefile to be the final target, such as ‘editor’ in the Example 1
  • When targets don’t exist, it uses commands to process the dependencies.
  • Updating files depend on the modified time of dependencies.
    • If the modified time is newer than the target’s, it recompiles and relinks. 
    • If the modified time is older than the target’s, it does not do anything.
  • phony targets:target that don’t need dependencies, just express action, such as ‘clean’. won’t create targets when compiling
    • execute commands in ‘clean’ 
    • $ make clean
  • If there exists a file called ‘clean’ in the directory
    • will create the ‘clean’ file
    • but ‘clean’ hasn’t any dependencies
    • ‘clean’ will be treated as the latest and never be executed
  • Let ‘clean’ be a phony target by “ .PHONY ”
    • It will not check whether the ‘clean’ file exist in the directory. 
    • Example
.PHONY:clean.
clean:
rm *.o
Basic Syntax of Makefile
  • Comment :start with ‘ # ’
  • Variable declare:MACRO = value
    • In variable names, uppercase and lowercase are different (case sensitive)
    • $(MACRO) or ${MACRO} access variable’s value
Example:
targets = foo
$(targets):common.h.
    gcc -o $(targets) foo.c 
equal to 
foo:common.h
    gcc -o foo foo.c
  • := :Variable’s value is assigned finally in the Makefile.
Example
x = foo.
y = $(x) bar
x = xyz
# y’s value is xyz bar
  • := indicate variable’s value is the value when it was defined.
Example
x := foo
y := $(x) bar
x := xyz
# y’s value is foo bar.

  • ?= syntax:If the variable was not defined, it is assigned a new value. If the variable was defined, it is original.
Example
FOO ?= bar
If FOO was not defined, its value is bar.
If FOO was defined, its value does not change.
  • += syntax:append new definition
Example
CFLAGS = -Wall -g.
CFLAGS += -O2. 
# CFLAGS’s value is -Wall -g -O2 

  • define syntax:
define foo
uname -a
echo $$SHELL
endef
all:
    $(foo)
equal to
foo = uname –a;echo $$SHELL.
all:
   $(foo)
Execution Result


  • @:don’t print the command when it is executed
  • - :the execution isn’t interrupted if the command has error  
Example
PHONY:clean. clean:
@echo "Clean...".     -rm *.o
  • if nothing be cleaned, it will return the error value to interrupt ‘make’
  • close the error interrupt function by ‘ - ’ 
Internal Variables(Automatic Variables)
  • $@:the file name of the target
  • $<:the name of the first dependency
  • $?:The names of all the dependencies are newer than the target, with spaces between them. 
  • $*:The file name of the target does not include the extension. 
Implicit Rules
  • According to the extension of target, ‘make’ will guess how to compile the target.
  • Makefile could be more concise.
Example
foo.o:common.h
gcc -c foo.c
Can be simplified to
foo.o:common.h

  • Empty commands could be used to avoid compiling with implicit rules.
Example
foo.o:common.h.
  <Tab>

Pattern Rules
  • The target contains the character ‘%’
    • the ‘%’ can match any nonempty substring 
    • such as ‘%.c’ can match any file name whose suffix is ‘.c’
main : main.o foo1.o foo2.o                                     
    ${CC} main.o foo1.o ${CFLAGS} ${INC} ${LIB} -o $@
%.o : %.c target.h                       
${CC} $< ${CFLAGS} ${INC} ${LIB} -lpthread -c  

  • Lack main.o, %.o is main.o, %.c is main.c, $< represents main.c, and then produce main.o .
  • Lack foo1.o or foo2.o, and so no.


Lab 2
  1. Practice different target files, and use the implicit rules.
  2. Add the ‘clean’ target to remove *.o and executable files.
  3. Create a ‘clean’ file in the directory, and test command          “make clean”.
  4. Edit the ‘clean’ target by ‘.PHONY’,  and test command       “make clean” again.
  5. Test the difference between ‘@rm’ and ‘–rm’. 

Lab 3
Edit testa.cc and testb.cc which prints “This is testa.” and “This is testb.” , respectively.
Test the example in next page, and modify it with ex.1 to ex.3  
 ex.1    x:=testa ex.2     x:=testa
     y:=$(x).o               y:=$(x).o
     x:=testb             x?=testb
 ex.3    x?=testa
     y?=$(x).o
     x?=testb
Modify the example with ‘$@’ and ‘$<’ . 

Reference
  • GNU `make‘, http://www.gnu.org/software/make/manual/make.html
  • http://tetralet.luna.com.tw/index.php?op=ViewArticle&articleId=185
  • http://maxubuntu.blogspot.com/2010/02/makefile.html
  • GNU Make Manual(Chinese translations), http://www.cc.ntut.edu.tw/~yccheng/oop2005f/GNUMakeManual.pdf
  • Make, wikipedia 
  • http://www.aka.org.cn/Lectures/001/Lecture-1/make.html
  • http://blog.xuite.net/jack_sb/2312/16268132
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