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林英超  副教授
Ing-Chao Lin, Associate Professor
Contact Info:
Email: iclin@mail.ncku.edu.tw
Tel: +886-62757575 ext. 62553
Office Location:
資訊系新館大樓11F 65B05
Lab Location: 資訊系新館大樓10F 65A02





SHORT BIO

Ing-Chao Lin is a faculty member in the department of Computer Science and Information Engineering, National Cheng Kung University since Feb 2009. He received his M.S. degree from Computer Science and Information Engineering Department, National Taiwan University , Taipei, Taiwan, and Ph.D. degree from Computer Science and Engineering Department, the Pennsylvania State University. Before joining CSIE, NCKU, he is a staff R & D Engineer in Real Intent, Inc, working on SDC frontend for Real Intent's automatic timing exception verifier. In his leisure time, he likes to spend time with his family and plays badminton and table tennis

EDUCATION

  • Ph.D., Department of Computer Science Engineering, The Pennsylvania State University
    • Dissertation: System Level Power and Reliability Modeling
    • Advisor: Dr. Vijay Narayanan, co-advised by Dr. Mary Jane Irwin
  • M.S., Department of Computer Science and Information Engineering, National Taiwan University
    • Advisor: Dr. Fei-pei Lai

RESEARCH INTEREST

Prof. Lin research interests focus on 
  • VLSI Design /System-on-Chip Design and Automation
  • Embedded System Design and Automation
  • Computer Architecture
  • Low Power System Design
  • Power Aware Reliable System Design

EXPERIENCE

  • Associate Professor, Department of CSIE, National Cheng-Kung University, Feb 2014
  • Assistant Professor, Department of CSIE, National Cheng-Kung University, Feb 2009- Jan 2014
  • Staff R&D Engineer, Real Intent, Sunnyvale, CA, USA, Oct 2007- Jan 2009
  • Teaching Assistant, Department of CSE, the Pennsylvania State University , Aug 2006 - Jan 2007
  • Research Assistant, Microsystems Design Lab, Department of CSE, the Pennsylvania State University, Jan 2005 - Jul 2006
  • Co-Op, IBM Hudson Valley Research Park , NY, USA, May 2004 - Dec 2004
  • Research Assistant, Microsystems Design Lab, Department of CSE, the Pennsylvania State University, Jan 2004 - May 2004
  • Teaching Assistant, Department of CSE, the Pennsylvania State University , Aug 2003 - Dec 2003

PUBLICATIONS

Journal
  • David Chang, Ing-Chao Lin, et al., "CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management", accepted by IEEE Trans. on Computer-Aided Design on Integrated Circuits (Regular paper, SCI)
  • Ing-Chao Lin*, et al., "High-Endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-Aware Policies", accepted by IEEE Trans. on VLSI (TVLSI) System (Regular paper, SCI)
  • Ing-Chao Lin* Yi-Ming Yang, "High-Performance Low-Power Carry Speculative Addition with Variable Latency", accepted by IEEE Trans. on VLSI (TVLSI) System (Regular paper, SCI)
  • Kai-Chiang Wu, Ing-Chao Lin*, and Yao-Te Wang, "BTI-aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs", accepted by IEEE Trans. on Computer-Aided Design on Integrated Circuits
  • Ing-Chao Lin*, Shun-Ming Syu, and Tsung-Yi Ho, "NBTI Tolerance and Leakage Reduction using Gate Sizing", accepted by ACM Journal on Emerging Technologies in Computing Systems"
  • Ing-Chao Lin*, Yu-Hung Cho, and Yi-Ming Yang, "Aging-Aware Reliable Multiplier With Adaptive Hold Logic", accepted by IEEE transaction on VLSI (TVLSI) Systems
  • Ing-Chao Lin*, Kuan-Hui Lee, Jia-Hao Lin, and Kai-Chiang Wu, "NBTI Mitigation and Leakage Reduction Using ILP-based Approach" accepted by IEEE transaction on VLSI (TVLS) Systems
  • Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, and Kuen-Jong Lee, “Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing,” in IEEE Trans. on Computer-Aided Design on Integrated Circuits, Vol. 33, No. 1, pp. 127-138 (Regular Paper )(EI, SCI) 
  • ŸIng-Chao Lin*, Chin-Hong Lin, and Kuan-Hui Li, “Leakage and Aging Optimization Using Transmission Gate-Based Technique”, in IEEE Trans. on Computer-Aided Design on Integrated Circuits, Vol. 32, No. 1, pp. 87-99, Jan. 2013 (EI, SCI)
  • N. Dhanwada, R. Bergamaschi2, W. Dungan, I. Nair, P. Gramann, W. Dougherty1 and I.-C. Lin, "Transaction-Level Modeling for Architectural and Power Analysis of PowerPC and CoreConnect based Systems," in Journal of Design Automation for Embedded Systems (JDAES '06)
Conference
  • N. Dhanwada, R. Bergamaschi, W. Dungan, I. Nair, W. Dougherty, Y. Shin, S. Bhattacharya, I. Lin, J. Darringer, S. Paliwa1, "Simultaneous Exploration of Power, Physical Design and Architectural Performance Dimensions of the SoC Design Space using SEAS", in IP Based SoC Design Forum & Exhibition, Dec 2004 (IP/REUSE 04 )
  • N. Dhanwada, I.-C. Lin and V. Narayanan, "A Power Estimation Methodology for SystemC Transaction Level Models," in Proceeding of International Conference on Hardware/Software Codesign and System Synthesis, Sep. 2005 (CODES+ISSS '05)
  • I.-C. Lin and V. Narayanan, "Transaction Level Power Modeling for PCI Express," in TECHCON, Oct. 2005 (TECHCON '05)
  • I.-C. Lin, S. Srinivasan, V. Narayanan, N. Dhanwada, "Transaction Level Error Susceptibility Model for Bus Based SoC Architectures," in Proceeding of International Symposium on Quality Electronic Design, Mar. 2006 (ISQED '06)
  • I.-C. Lin and V. Narayanan, "System Level Power and Reliability Modeling," Ph.D. Forum, Design, Automation and Test in Europe Conference and Exhibition, Apr. 2007 (DATE '07)
  • Shi-Qun Zheng and Ing-Chao Lin, "Transaction-level error susceptibility for bus-based System-on-Chip: From single-bit to multi-bit," in Proceedings of International Computer Symposium (ICS), 2010 International , pp.670-675, 2010
  • Shi-Qun Zheng, Ing-Chao Lin, and Yen-Han Lee, “Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect”, in Proceedings of Great Lakes Symposium on VLSI (GLSVLSI'2011) pp. 415-418, 2011
  • Yu-Hung Cho, Ing-Chao Lin, and Yi-Ming Yang, "Aging-aware reliable multiplier design," in Proceedings of SOC Conference (SOCC), pp.322,327, 12-14 Sept. 2012
  • Kuan-Hui Li, C.-H. Lin, and I.-C. Lin, “TG-based Technique for NBTI Degradation and Leakage Optimization“ in Proceedings of VLSI/CAD Symposium, 2011
  • Shi-Qun Zheng, I.-C. Lin, “Mitigating NBTI using Core Rotation and Scheduled Voltage Scaling“ in Proc. of VLSI/CAD Symposium, Aug. 2011
  • Chin-Hung Lin, Ing-Chao Lin and Kuan-Hui Li, "TG-based technique for NBTI degradation and leakage optimization," in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp.133,138, 1-3 Aug. 2011
  • Kuan-Hui Li, Ing-Chao Lin Li, and Jia-Hao Lin, "NBTI Mitigation and Leakage Reduction Using ILP" in Proceedings of VLSI/CAD Symposium, Aug. 2012
  • Yao-Te Wang and Ing-Chao Lin, "Analyzing BTI effects on retention registers," In Proceedings of Asia Symposium of Quality Electronic Design (ASQED), pp.71-77, Jul. 2012 (EI)
  • Yan-Han Lee, Ing-Chao Lin, and Shen-Wei Wang, “Impact of NBTI and PBTI effects on Ternary CAM”, To appear in ISQED 2013 (EI)
  • Shun-Ming Syu, Yu-Hui Shao, and Ing-Chao Lin, "High-endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-aware Policy", in Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. 19-24, May 2013
HONOR AND AWARDS
  • 2013/11 古全鈞、魏廷穎 教育部智慧電子跨領域應用專題系列課程計畫之4C電子領域競賽—優良專題作品組 
  • 2013/12 指導學生李怡樺論文榮獲2013 IEEE Tainan Section 最佳碩士論文獎
  • 2013/10 指導學生李怡樺論文榮獲2013 TIEEE 最佳博碩士論文 優等獎
  • 2013 指導學生張鶴騰參加教育部2013 CAD Contest 獲得定題組特優
  • 2013 指導學生王耀德論文榮獲中華民國資訊學會 2013最佳碩士論文獎 佳作
  • 2013 指導學生許順明論文榮獲中華民國資訊學會 2013最佳碩士論文獎 佳作
  • 2013 指導學生許順明論文獲選為VLSI/CAD Symposium Best Paper Award Candidate
  • 2012 指導學生張鶴騰及林家豪參加教育部2012 CAD Contest 獲得 平台開發組特優
  • 2012 指導獲得教育部主辦之電腦補助軟體設計競賽(CAD Contest) 獲得平台開發組 最佳指導教授奬
  • 2012 指導學生楊顗民論文榮獲全研科技論文奬金研奬
  • 2012 指導學生卓育弘論文獲得VLSI/CAD Symposium Best Paper Award Candidate
  • 2012 指導學生卓育弘論文榮獲中華民國資訊學會 2012最佳碩士論文獎 佳作
  • 2010 指導學生黃崇蔚 ACM ICPC 合肥站佳作

ADVICE

FUNDING

  • 國科會 Handling SOC Bus Degradation due to NBTI and HCE, NSC 98-2218-E-006-237-
  • 國科會 Aging Analysis of SoC Bus Degradation, NSC 99-2221-E-006-222
  • 國立成功大學優秀新進教師計畫
  • 國立成功大學外語授課計畫 (97年第二學期, 98年第一學期, 98年第二學期, 99年第一學期)
  • 教育部跨學門科學人才培育計畫 (99.1~99.12)
  • 國立成功大學電資學院一流大學新進教師計畫 (98.1~)
  • 雲嘉南區域教學資源中心教師專業成長社群 (98)

SERVICE

  • Talk in NCTU
  • Talk in NFU
  • DAC Conference Paper Reviewer
  • ICCAD Conference Paper Reviewer
  • VLSI/CAD Conference Paper Reviewer
  • ICECS Conference Paper Reviewer
  • TCAD Journal Paper Reviewer
  • TVLSI Journal Paper Reviewer
  • JCIE Journal Paper Reviwer
  • EURASIP Journal Paper Reviewer
  • Session Chair VLSI/CAD (2010), ICS (2010), ISDLT (2009, 2010)
Ċ
Ing-Chao Lin,
Oct 18, 2017, 10:34 PM
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